/*
 * Copyright (c) 2019, Cvitek. All rights reserved.
 *
 */
// Generate Time stamp is : 2019-11-27 20:20:28
#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
#define JTAG_CPU_TCK__DBG_1 1
#define JTAG_CPU_TCK__XGPIOA_0 3
#define SDIO0_CD__SDIO0_CD 0
#define SDIO0_CD__DBG_6 1
#define SDIO0_CD__XGPIOA_1 3
#define RSTN__RSTN 0
#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
#define JTAG_CPU_TRST__DBG_0 1
#define JTAG_CPU_TRST__XGPIOA_2 3
#define UART0_RX__UART0_RX 0
#define UART0_RX__DBG_4 1
#define UART0_RX__AUX0 2
#define UART0_RX__XGPIOA_3 3
#define UART0_RX__H265_UART_RX 4
#define UART0_RX__H264_UART_RX 5
#define SDIO0_PWR_EN__SDIO0_PWR_EN 0
#define SDIO0_PWR_EN__DBG_5 1
#define SDIO0_PWR_EN__XGPIOA_4 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__DBG_3 1
#define UART0_TX__AUX1 2
#define UART0_TX__XGPIOA_5 3
#define UART0_TX__H265_UART_TX 4
#define UART0_TX__H264_UART_TX 5
#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
#define JTAG_CPU_TMS__DBG_2 1
#define JTAG_CPU_TMS__XGPIOA_6 3
#define JTAG_CPU_TMS__JTAG_CPU_5W_TMS 4
#define EMMC_CLK__EMMC_CLK 0
#define EMMC_CLK__SPINOR_SCK 1
#define EMMC_CLK__SPINAND_CLK 2
#define EMMC_CLK__XGPIOA_7 3
#define EMMC_RSTN__EMMC_RSTN 0
#define EMMC_RSTN__XGPIOA_8 3
#define EMMC_RSTN__AUX2 4
#define EMMC_RSTN__IIS2_MCLK 5
#define EMMC_CMD__EMMC_CMD 0
#define EMMC_CMD__SPINOR_SDI 1
#define EMMC_CMD__SPINAND_DI 2
#define EMMC_CMD__XGPIOA_9 3
#define EMMC_DAT1__EMMC_DAT_1 0
#define EMMC_DAT1__SPINOR_CS_X 1
#define EMMC_DAT1__SPINAND_CS 2
#define EMMC_DAT1__XGPIOA_10 3
#define EMMC_DAT0__EMMC_DAT_0 0
#define EMMC_DAT0__SPINOR_SDO 1
#define EMMC_DAT0__SPINAND_DO 2
#define EMMC_DAT0__XGPIOA_11 3
#define EMMC_DAT2__EMMC_DAT_2 0
#define EMMC_DAT2__SPINOR_HOLD_X 1
#define EMMC_DAT2__SPINAND_HOLD 2
#define EMMC_DAT2__XGPIOA_12 3
#define EMMC_DAT3__EMMC_DAT_3 0
#define EMMC_DAT3__SPINOR_WP_X 1
#define EMMC_DAT3__SPINAND_WP 2
#define EMMC_DAT3__XGPIOA_13 3
#define SDIO0_CMD__SDIO0_CMD 0
#define SDIO0_CMD__DBG_11 1
#define SDIO0_CMD__XGPIOA_14 3
#define SDIO0_CLK__SDIO0_CLK 0
#define SDIO0_CLK__DBG_12 1
#define SDIO0_CLK__XGPIOA_15 3
#define SDIO0_D0__SDIO0_D_0 0
#define SDIO0_D0__DBG_10 1
#define SDIO0_D0__XGPIOA_16 3
#define SDIO0_D1__SDIO0_D_1 0
#define SDIO0_D1__DBG_9 1
#define SDIO0_D1__XGPIOA_17 3
#define SDIO0_D2__SDIO0_D_2 0
#define SDIO0_D2__DBG_8 1
#define SDIO0_D2__AUX0 2
#define SDIO0_D2__XGPIOA_18 3
#define SDIO0_D3__SDIO0_D_3 0
#define SDIO0_D3__DBG_7 1
#define SDIO0_D3__AUX1 2
#define SDIO0_D3__XGPIOA_19 3
#define RMII0_TXEN__RMII0_TXEN 0
#define RMII0_TXEN__UART1_TX 1
#define RMII0_TXEN__UART2_TX 2
#define RMII0_TXEN__XGPIOA_20 3
#define RMII0_TXEN__H265_UART_TX 4
#define RMII0_TXEN__IIS2_DI 5
#define RMII0_TXEN__H264_UART_TX 6
#define RMII0_TXEN__WG1_D0 7
#define RMII0_TXD1__RMII0_TXD1 0
#define RMII0_TXD1__UART1_RX 1
#define RMII0_TXD1__UART2_RX 2
#define RMII0_TXD1__XGPIOA_21 3
#define RMII0_TXD1__H265_UART_RX 4
#define RMII0_TXD1__IIS2_DO 5
#define RMII0_TXD1__H264_UART_RX 6
#define RMII0_TXD1__WG1_D1 7
#define RMII0_TXD0__RMII0_TXD0 0
#define RMII0_TXD0__UART1_CTS 1
#define RMII0_TXD0__UART2_CTS 2
#define RMII0_TXD0__XGPIOA_22 3
#define RMII0_TXD0__IIS2_LRCK 5
#define RMII0_TXD0__UART4_TX 6
#define RMII0_TXD0__EPHY_SPD_LED 7
#define RMII0_REFCLKI__RMII0_REFCLKI 0
#define RMII0_REFCLKI__SDIO1_D_0 1
#define RMII0_REFCLKI__SPI1_SDI 2
#define RMII0_REFCLKI__XGPIOA_23 3
#define RMII0_REFCLKI__EPHY_DPX_LED 6
#define RMII0_MDIO__RMII0_MDIO 0
#define RMII0_MDIO__SDIO1_CMD 1
#define RMII0_MDIO__SPI1_SDO 2
#define RMII0_MDIO__XGPIOA_24 3
#define RMII0_MDIO__EPHY_SPD_LED 6
#define RMII0_MDCK__RMII0_MDC 0
#define RMII0_MDCK__SDIO1_CLK 1
#define RMII0_MDCK__SPI1_SCK 2
#define RMII0_MDCK__XGPIOA_25 3
#define RMII0_MDCK__EPHY_LNK_LED 6
#define RMII0_RST__UART1_RTS 1
#define RMII0_RST__UART2_RTS 2
#define RMII0_RST__XGPIOA_26 3
#define RMII0_RST__RMII0_IRQ 4
#define RMII0_RST__IIS2_BCLK 5
#define RMII0_RST__UART4_RX 6
#define RMII0_RST__EPHY_LNK_LED 7
#define RMII0_RXD0__RMII0_RXD0 0
#define RMII0_RXD0__SDIO1_D_2 1
#define RMII0_RXD0__XGPIOA_27 3
#define RMII0_RXD0__H265_UART_TX 4
#define RMII0_RXD0__EPHY_DPX_LED 6
#define RMII0_RXD0__H264_UART_TX 7
#define RMII0_RXD1__RMII0_RXD1 0
#define RMII0_RXD1__SDIO1_D_1 1
#define RMII0_RXD1__XGPIOA_28 3
#define RMII0_RXD1__H265_UART_RX 4
#define RMII0_RXD1__EPHY_SPD_LED 6
#define RMII0_RXD1__H264_UART_RX 7
#define RMII0_RXDV__RMII0_RXDV 0
#define RMII0_RXDV__SDIO1_D_3 1
#define RMII0_RXDV__SPI1_CS_X 2
#define RMII0_RXDV__XGPIOA_29 3
#define RMII0_RXDV__EPHY_LNK_LED 6
#define RTC_MODE__RTC_MODE 0
#define RTC_MODE__XGPIOA_30 3
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__XGPIOA_31 3
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__XGPIOB_0 3
#define PWR_WAKEUP1__PWR_WAKEUP1 0
#define PWR_WAKEUP1__XGPIOB_1 3
#define PWR_BUTTON0__PWR_BUTTON0 0
#define PWR_BUTTON0__XGPIOD_11 3
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_ON__PWR_ON 0
#define PWR_ON__XGPIOB_2 3
#define PTEST__PTEST 0
#define PWM2__PWM_2 0
#define PWM2__IIC1_SCL 1
#define PWM2__KEY_COL2 2
#define PWM2__XGPIOB_3 3
#define PWM2__JTAG_CPU_5W_TDI 4
#define PWM2__UART3_RX 5
#define PWM2__WG2_D0 7
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_6 3
#define PWM3__PWM_3 0
#define PWM3__IIC1_SDA 1
#define PWM3__KEY_COL3 2
#define PWM3__XGPIOB_5 3
#define PWM3__UART3_TX 5
#define PWM3__WG2_D1 7
#define PWM1__PWM_1 0
#define PWM1__XGPIOB_4 3
#define PWM1__JTAG_CPU_5W_TDO 4
#define SPI0_SDI__SPI0_SDI 0
#define SPI0_SDI__IIC2_SDA 1
#define SPI0_SDI__PWM_15 2
#define SPI0_SDI__XGPIOB_8 3
#define SPI0_SDI__UART3_CTS 4
#define SPI0_SDI__RMII1_TXD3 5
#define SPI0_SDI__SPINOR1_SDI 6
#define SPI0_SDO__SPI0_SDO 0
#define SPI0_SDO__IIC2_SCL 1
#define SPI0_SDO__PWM_14 2
#define SPI0_SDO__XGPIOB_10 3
#define SPI0_SDO__UART3_RTS 4
#define SPI0_SDO__RMII1_RXD3 5
#define SPI0_SDO__SPINOR1_SDO 6
#define SPI0_SCK__SPI0_SCK 0
#define SPI0_SCK__IIC4_SCL 1
#define SPI0_SCK__PWM_12 2
#define SPI0_SCK__XGPIOB_7 3
#define SPI0_SCK__UART3_RX 4
#define SPI0_SCK__RMII1_TXD2 5
#define SPI0_SCK__SPINOR1_SCK 6
#define SPI0_CS_X__SPI0_CS_X 0
#define SPI0_CS_X__IIC4_SDA 1
#define SPI0_CS_X__PWM_13 2
#define SPI0_CS_X__XGPIOB_9 3
#define SPI0_CS_X__UART3_TX 4
#define SPI0_CS_X__RMII1_RXD2 5
#define SPI0_CS_X__SPINOR1_CS_X 6
#define IIC2_SCL__IIC2_SCL 0
#define IIC2_SCL__PWM_14 1
#define IIC2_SCL__UART2_RX 2
#define IIC2_SCL__XGPIOB_11 3
#define IIC2_SCL__RMII1_MDIO 4
#define IIC1_SCL__IIC1_SCL 0
#define IIC1_SCL__PWM_12 1
#define IIC1_SCL__XGPIOB_12 3
#define IIC1_SCL__RMII1_RXD1 4
#define IIC1_SCL__SPINOR1_HOLD_X 6
#define IIC1_SDA__IIC1_SDA 0
#define IIC1_SDA__PWM_13 1
#define IIC1_SDA__XGPIOB_14 3
#define IIC1_SDA__RMII1_REFCLKI 4
#define IIC1_SDA__SPINOR1_WP_X 6
#define UART2_TX__UART2_TX 0
#define UART2_TX__PWM_11 1
#define UART2_TX__KEY_ROW3 2
#define UART2_TX__XGPIOB_15 3
#define UART2_TX__RMII1_RXD0 4
#define UART2_TX__WG2_D0 7
#define IIC2_SDA__IIC2_SDA 0
#define IIC2_SDA__PWM_15 1
#define IIC2_SDA__UART2_TX 2
#define IIC2_SDA__XGPIOB_13 3
#define IIC2_SDA__RMII1_MDC 4
#define UART1_RTS__UART1_RTS 0
#define UART1_RTS__PWM_7 1
#define UART1_RTS__KEY_COL1 2
#define UART1_RTS__XGPIOB_16 3
#define UART1_RTS__RMII1_TXD0 4
#define UART1_RTS__IIS1_DI 5
#define UART1_RTS__UART4_TX 7
#define UART2_RTS__UART2_RTS 0
#define UART2_RTS__PWM_8 1
#define UART2_RTS__KEY_ROW0 2
#define UART2_RTS__XGPIOB_18 3
#define UART2_RTS__RMII1_TXD1 4
#define UART2_RTS__IIS1_MCLK 5
#define UART2_RTS__WG1_D0 7
#define UART2_RX__UART2_RX 0
#define UART2_RX__PWM_10 1
#define UART2_RX__KEY_COL3 2
#define UART2_RX__XGPIOB_17 3
#define UART2_RX__RMII1_RXDV 4
#define UART2_RX__WG2_D1 7
#define UART1_TX__UART1_TX 0
#define UART1_TX__PWM_4 1
#define UART1_TX__KEY_COL2 2
#define UART1_TX__XGPIOB_21 3
#define UART1_TX__RMII1_TXCLK 4
#define UART1_TX__IIS1_BCLK 5
#define UART1_TX__EPHY_LNK_LED 7
#define UART1_CTS__UART1_CTS 0
#define UART1_CTS__PWM_6 1
#define UART1_CTS__KEY_COL0 2
#define UART1_CTS__XGPIOB_20 3
#define UART1_CTS__IIS1_DO 5
#define UART1_CTS__RMII1_IRQ 6
#define UART1_CTS__UART4_RX 7
#define BOOT_MS__BOOT_MS 0
#define BOOT_MS__XGPIOB_22 3
#define UART2_CTS__UART2_CTS 0
#define UART2_CTS__PWM_9 1
#define UART2_CTS__KEY_ROW1 2
#define UART2_CTS__XGPIOB_19 3
#define UART2_CTS__RMII1_TXEN 4
#define UART2_CTS__WG1_D1 7
#define ADC1__XGPIOB_24 3
#define UART1_RX__UART1_RX 0
#define UART1_RX__PWM_5 1
#define UART1_RX__KEY_ROW2 2
#define UART1_RX__XGPIOB_23 3
#define UART1_RX__IIS1_LRCK 5
#define UART1_RX__EPHY_SPD_LED 7
#define USB_ID__USB_ID 0
#define USB_ID__XGPIOB_26 3
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_25 3
#define USB_VBUS_EN__USB_VBUS_EN 0
#define USB_VBUS_EN__XGPIOB_27 3
#define CLK32K__CLK32K 0
#define CLK32K__AUX0 1
#define CLK32K__DBG_1 2
#define CLK32K__XGPIOB_29 3
#define CLK25M__CLK25M 0
#define CLK25M__AUX1 1
#define CLK25M__DBG_0 2
#define CLK25M__XGPIOB_28 3
#define XTAL_XIN_XI__XTAL_CLKIN 0
#define VO_DATA1__VO_DATA_1 1
#define VO_DATA1__XGPIOC_8 3
#define VO_DATA1__VO_BUS_1 6
#define VO_DATA0__VO_DATA_0 1
#define VO_DATA0__XGPIOC_9 3
#define VO_DATA0__VO_BUS_0 6
#define PAD_MIPI_TXM4__VO_DATA_10 1
#define PAD_MIPI_TXM4__DBG_13 2
#define PAD_MIPI_TXM4__XGPIOB_30 3
#define PAD_MIPI_TXM4__SPI3_SCK 4
#define PAD_MIPI_TXM4__PWM_12 5
#define PAD_MIPI_TXM4__VO_BUS_10 6
#define PAD_MIPI_TXP4__VO_DATA_9 1
#define PAD_MIPI_TXP4__DBG_14 2
#define PAD_MIPI_TXP4__XGPIOB_31 3
#define PAD_MIPI_TXP4__SPI3_CS_X 4
#define PAD_MIPI_TXP4__PWM_13 5
#define PAD_MIPI_TXP4__VO_BUS_9 6
#define PAD_MIPI_TXM3__VO_DATA_8 1
#define PAD_MIPI_TXM3__DBG_15 2
#define PAD_MIPI_TXM3__XGPIOC_0 3
#define PAD_MIPI_TXM3__SPI3_SDO 4
#define PAD_MIPI_TXM3__PWM_6 5
#define PAD_MIPI_TXM3__VO_BUS_8 6
#define PAD_MIPI_TXP3__VO_DATA_7 1
#define PAD_MIPI_TXP3__DBG_16 2
#define PAD_MIPI_TXP3__XGPIOC_1 3
#define PAD_MIPI_TXP3__SPI3_SDI 4
#define PAD_MIPI_TXP3__PWM_7 5
#define PAD_MIPI_TXP3__VO_BUS_7 6
#define PAD_MIPI_TXM2__VO_DATA_6 1
#define PAD_MIPI_TXM2__DBG_17 2
#define PAD_MIPI_TXM2__XGPIOC_2 3
#define PAD_MIPI_TXM2__KEY_ROW0 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__VO_BUS_6 6
#define PAD_MIPI_TXP2__VO_DATA_5 1
#define PAD_MIPI_TXP2__DBG_18 2
#define PAD_MIPI_TXP2__XGPIOC_3 3
#define PAD_MIPI_TXP2__KEY_ROW1 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__VO_BUS_5 6
#define PAD_MIPI_TXM1__VO_DATA_4 1
#define PAD_MIPI_TXM1__DBG_19 2
#define PAD_MIPI_TXM1__XGPIOC_4 3
#define PAD_MIPI_TXM1__KEY_ROW2 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__VO_BUS_4 6
#define PAD_MIPI_TXP1__VO_DATA_3 1
#define PAD_MIPI_TXP1__DBG_20 2
#define PAD_MIPI_TXP1__XGPIOC_5 3
#define PAD_MIPI_TXP1__KEY_ROW3 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__VO_BUS_3 6
#define PAD_MIPI_TXM0__VO_DATA_2 1
#define PAD_MIPI_TXM0__DBG_21 2
#define PAD_MIPI_TXM0__XGPIOC_6 3
#define PAD_MIPI_TXM0__KEY_COL0 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__VO_BUS_2 6
#define PAD_MIPI_TXP0__VO_CLK 1
#define PAD_MIPI_TXP0__DBG_22 2
#define PAD_MIPI_TXP0__XGPIOC_7 3
#define PAD_MIPI_TXP0__KEY_COL1 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__VO_BUS_11 6
#define MIPIRX1_PAD0P__VI_DATA_0 1
#define MIPIRX1_PAD0P__DBG_0 2
#define MIPIRX1_PAD0P__XGPIOC_10 3
#define MIPIRX1_PAD0P__VO_DATA_11 4
#define MIPIRX1_PAD0P__VI1_DATA_8 5
#define MIPIRX1_PAD0P__VO_BUS_12 6
#define MIPIRX1_PAD0N__VI_DATA_1 1
#define MIPIRX1_PAD0N__DBG_31 2
#define MIPIRX1_PAD0N__XGPIOC_11 3
#define MIPIRX1_PAD0N__VO_DATA_12 4
#define MIPIRX1_PAD0N__VI1_DATA_7 5
#define MIPIRX1_PAD0N__VO_BUS_13 6
#define MIPIRX1_PAD1P__VI_DATA_2 1
#define MIPIRX1_PAD1P__DBG_30 2
#define MIPIRX1_PAD1P__XGPIOC_12 3
#define MIPIRX1_PAD1P__VO_DATA_13 4
#define MIPIRX1_PAD1P__VI1_DATA_6 5
#define MIPIRX1_PAD1P__VO_BUS_14 6
#define MIPIRX1_PAD1N__VI_DATA_3 1
#define MIPIRX1_PAD1N__DBG_29 2
#define MIPIRX1_PAD1N__XGPIOC_13 3
#define MIPIRX1_PAD1N__VO_DATA_14 4
#define MIPIRX1_PAD1N__VI1_DATA_5 5
#define MIPIRX1_PAD1N__VO_BUS_15 6
#define MIPIRX1_PAD2P__VI_DATA_4 1
#define MIPIRX1_PAD2P__DBG_28 2
#define MIPIRX1_PAD2P__XGPIOC_14 3
#define MIPIRX1_PAD2P__VO_DATA_15 4
#define MIPIRX1_PAD2P__VI1_DATA_4 5
#define MIPIRX1_PAD2P__VO_BUS_16 6
#define MIPIRX1_PAD2N__VI_DATA_5 1
#define MIPIRX1_PAD2N__DBG_27 2
#define MIPIRX1_PAD2N__XGPIOC_15 3
#define MIPIRX1_PAD2N__VO_DATA_16 4
#define MIPIRX1_PAD2N__VI1_DATA_3 5
#define MIPIRX1_PAD2N__VO_BUS_17 6
#define MIPIRX1_PAD3P__VI_DATA_6 1
#define MIPIRX1_PAD3P__DBG_26 2
#define MIPIRX1_PAD3P__XGPIOC_16 3
#define MIPIRX1_PAD3P__VO_DATA_17 4
#define MIPIRX1_PAD3P__VI1_DATA_2 5
#define MIPIRX1_PAD3P__VO_BUS_18 6
#define MIPIRX1_PAD3N__VI_DATA_7 1
#define MIPIRX1_PAD3N__DBG_25 2
#define MIPIRX1_PAD3N__XGPIOC_17 3
#define MIPIRX1_PAD3N__VI1_DATA_1 5
#define MIPIRX1_PAD4P__VI_DATA_8 1
#define MIPIRX1_PAD4P__DBG_24 2
#define MIPIRX1_PAD4P__XGPIOC_18 3
#define MIPIRX1_PAD4P__VI1_DATA_0 5
#define MIPIRX1_PAD4N__VI_DATA_9 1
#define MIPIRX1_PAD4N__DBG_23 2
#define MIPIRX1_PAD4N__XGPIOC_19 3
#define MIPIRX1_PAD4N__VI1_CLK 5
#define MIPIRX0_PAD4N__VI_DATA_10 1
#define MIPIRX0_PAD4N__DBG_1 2
#define MIPIRX0_PAD4N__XGPIOC_20 3
#define MIPIRX0_PAD4N__VI1_DATA_9 5
#define MIPIRX0_PAD4P__VI_DATA_11 1
#define MIPIRX0_PAD4P__DBG_2 2
#define MIPIRX0_PAD4P__XGPIOC_21 3
#define MIPIRX0_PAD3N__VI_DATA_12 1
#define MIPIRX0_PAD3N__DBG_4 2
#define MIPIRX0_PAD3N__XGPIOC_23 3
#define MIPIRX0_PAD3P__VI_CLK 1
#define MIPIRX0_PAD3P__DBG_3 2
#define MIPIRX0_PAD3P__XGPIOC_22 3
#define MIPIRX0_PAD2N__VI_DATA_13 1
#define MIPIRX0_PAD2N__DBG_5 2
#define MIPIRX0_PAD2N__XGPIOC_24 3
#define MIPIRX0_PAD2N__IIC4_SCL 4
#define MIPIRX0_PAD2P__VI_DATA_14 1
#define MIPIRX0_PAD2P__DBG_6 2
#define MIPIRX0_PAD2P__XGPIOC_25 3
#define MIPIRX0_PAD2P__IIC4_SDA 4
#define MIPIRX0_PAD1N__VI_DATA_15 1
#define MIPIRX0_PAD1N__DBG_7 2
#define MIPIRX0_PAD1N__XGPIOC_26 3
#define MIPIRX0_PAD1N__KEY_ROW3 4
#define MIPIRX0_PAD1P__VI_DATA_16 1
#define MIPIRX0_PAD1P__DBG_8 2
#define MIPIRX0_PAD1P__XGPIOC_27 3
#define MIPIRX0_PAD1P__KEY_ROW2 4
#define MIPIRX0_PAD0N__VI_DATA_17 1
#define MIPIRX0_PAD0N__DBG_9 2
#define MIPIRX0_PAD0N__XGPIOC_28 3
#define MIPIRX0_PAD0P__VI_DATA_18 1
#define MIPIRX0_PAD0P__DBG_10 2
#define MIPIRX0_PAD0P__XGPIOC_29 3
#define VI_DATA22__VI_DATA_22 1
#define VI_DATA22__DBG_14 2
#define VI_DATA22__XGPIOC_30 3
#define VI_DATA22__KEY_COL1 4
#define VI_DATA22__UART3_TX 5
#define VI_DATA22__H265_UART_TX 6
#define VI_DATA22__H264_UART_TX 7
#define VI_DATA20__VI_DATA_20 1
#define VI_DATA20__DBG_12 2
#define VI_DATA20__XGPIOC_31 3
#define VI_DATA20__KEY_ROW0 4
#define VI_DATA21__VI_DATA_21 1
#define VI_DATA21__DBG_13 2
#define VI_DATA21__XGPIOD_0 3
#define VI_DATA21__KEY_COL0 4
#define VI_DATA21__UART3_RX 5
#define VI_DATA21__H265_UART_RX 6
#define VI_DATA21__H264_UART_RX 7
#define CAM_PD0__CAM_MCLK1 0
#define CAM_PD0__AUX2 2
#define CAM_PD0__XGPIOD_1 3
#define VI_DATA19__VI_DATA_19 1
#define VI_DATA19__DBG_11 2
#define VI_DATA19__XGPIOD_2 3
#define VI_DATA19__KEY_ROW1 4
#define IIC0_SDA__IIC0_SDA 0
#define IIC0_SDA__SPI2_SDO 1
#define IIC0_SDA__XGPIOD_3 3
#define CAM_MCLK0__CAM_MCLK0 0
#define CAM_MCLK0__AUX3 2
#define CAM_MCLK0__XGPIOD_4 3
#define IIC3_SCL__IIC3_SCL 0
#define IIC3_SCL__SPI2_SCK 1
#define IIC3_SCL__DBG_17 2
#define IIC3_SCL__XGPIOD_5 3
#define IIC3_SCL__IIC4_SCL 4
#define VI_DATA24__VI_DATA_24 1
#define VI_DATA24__DBG_16 2
#define VI_DATA24__XGPIOD_6 3
#define VI_DATA24__KEY_COL3 4
#define VI_DATA24__UART3_CTS 5
#define CAM_RST0__XGPIOD_7 3
#define VI_DATA23__VI_DATA_23 1
#define VI_DATA23__DBG_15 2
#define VI_DATA23__XGPIOD_8 3
#define VI_DATA23__KEY_COL2 4
#define VI_DATA23__UART3_RTS 5
#define IIC3_SDA__IIC3_SDA 0
#define IIC3_SDA__SPI2_CS_X 1
#define IIC3_SDA__DBG_18 2
#define IIC3_SDA__XGPIOD_9 3
#define IIC3_SDA__IIC4_SDA 4
#define IIC0_SCL__IIC0_SCL 0
#define IIC0_SCL__SPI2_SDI 1
#define IIC0_SCL__XGPIOD_10 3
